| 公告主旨 |
【Joint CQSE & NCTS Seminar】2026-03-27 Weight-four parity checks with silicon spin qubits |
| 公告內容 |
Time: March 27, 14:30 ~ 15:30
Title: Weight-four parity checks with silicon spin qubits
Speaker: Dr. Yi-Hsien Wu （Postdoctoral researcher, TU Delft）
Place: Rm. 104, Chin-Pao Yang Lecture Hall, Department of Physics/CCMS, NTU
Online Link: https://nationaltaiwanuniversity-zbh.my.webex.com/nationaltaiwanuniversity-zbh.my/j.php?MTID=madb2c3b9d23a56faace3593823ecfdee
Abstract:
Weight-four parity checks with silicon spin qubits
Brennan Undseth1,*, Nicola Meggiato1,*, Yi-Hsien Wu1,#, Sam R. Katiraee-Far1, Larysa Tryputen2,
Sander L. de Snoo1, Davide Degli Esposti1, Giordano Scappucci1, Eliška Greplová1 and Lieven M. K. Vandersypen1
1QuTech and Kavli Institute of Nanoscience, Delft University of Technology, Lorentzweg 1, 2628 CJ Delft, The Netherlands
2Netherlands Organization for Applied Scientific Research （TNO）, Stieltjesweg 1, 2628 CK Delft, Netherlands
*These authors contributed equally to this work.
#Presenter
Spin qubit arrays are scaling up and showing the potential to realize large-scale quantum computing. The recently demonstrated ability to shuttle spin qubits with high fidelity [1] opens the possibility of operating large-scale spin qubit devices in a reconfigurable fashion. Here, we demonstrate a device containing a bi-linear array [2, 3], consisting of a shuttling channel for moving an ancilla qubit and an array of sparsely separated data qubits.
The device contains four quantum dots hosting data qubits, which we call "bus stops." These qubits are spaced over a 500 nm range to avoid residual coupling. A conveyor “bus” channel next to the data qubit array allows an ancilla qubit to be shuttled to each of the four bus stops, enabling entangling operations between the ancilla and any data qubit. This allows for all-to-all connectivity among the data qubits via the ancilla. The ancilla is read out using Pauli spin blockade （PSB） by projecting to a fixed reference qubit at the left end of the shuttling channel. A nearby charge sensor is used to detect this PSB signal. Because the sensors sensing range only reaches the first bus stop, we use the spin signal of the shuttled ancilla to tune the population and virtual gates of the other bus stop qubits. Once a bus stop is loaded, we load another electron from the charge sensor and repeat the process until all bus stops are filled. The bus stop qubits are read out by performing quantum non-demolition （QND） readout with the ancilla. We tune single-qubit operations for all qubits and two-qubit operations between the ancilla and the bus stops, yielding universal control of an effective five-qubit processor.
We performed X- and Z-parity checks up to weight-4 between the ancilla and the bus stop qubits. The parity check circuits are then used to generate genuine multi-partite entangled states for up to five qubits. The ability to generate five-qubit entangled states also allows for logical state generation with X-parity checks. By measuring and post-selecting the ancilla qubit outcome, we observed two different GHZ states with the expected 0 or phase. This observation is essential for performing feedback correction on the logical qubit state. These results pave the way for operating future large-scale sparse qubit arrays and performing logical state stabilization through repetitive parity checks [4].
References
[1] De Smet, M. et al., Nat. Nanotechnol. 20, 866–872 （2025）
[2] Taylor, J. et al., Nature Phys 1, 177–183 （2005）
[3] Undseth, B., Meggiato, N., et. al., arXiv: arXiv:2601.23267 （2026）
[4] Andersen, C.K. et. al., Nat. Phys., 16, 875–880 （2020）
Biography:
Yi-Hsien Wu is an experimental physicist interested in realizing quantum computers with spin qubits in silicon devices. He received his Ph.D. from National Taiwan University in 2025. During his Ph.D., he worked on the high-fidelity control of quantum dot spin qubits while visiting RIKEN in Japan as an International Program Associate. He is now a postdoctoral researcher at TU Delft in the Netherlands, where he researches spin qubit architectures for large-scale devices
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